View 83C694_4432798.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

twisted-pair interface and manchester encoder/decoder 83C694d data sheet
table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 document scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 manchester encoder/differential driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 manchester decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 collision translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.5 tp differential driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 tp differential receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.7 loopback function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.8 link test function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9 aui/tp autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.10 jabber and sqe test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.11 status indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.12 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.0 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 dc operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 ac operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.0 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 83C694d i
list of illustrations figure title page 1-1 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1-2 83C694c block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2-1 crystal connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2-2 aui transmit path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2-3 aui receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2-4 zener diode voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2-5 twisted pair transmit path and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-6 twisted pair receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3-1 83C694c plcc package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5-1 transmit timing - start of transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5-2 transmit timing - end of transmission (last bit = 0) . . . . . . . . . . . . . . . . . 21 5-3 transmit timing - end of transmission (last bit = 1) . . . . . . . . . . . . . . . . . 22 5-4 transmit timing - link test pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5-5 receive timing - start of packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5-6 receive timing - end of packet (last bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 23 5-7 receive timing - end of packet (last bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 24 5-8 collision timing (aui) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5-9 collision timing (tp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5-10 sqe test timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5-11 loopback timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5-11 test loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6-1 44-pin plcc package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 list of tables table title page 3-1 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4-1 dc operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5-1 ac operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5-2 83C694c timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 83C694d ii
1.0 introduction 1.1 document scope this document describes the function and opera- tion of the 83C694d twisted-pair interface and manchester encoder/decoder. it includes a de- scription of external logic necessary for the efficient use of this device and its proper role in the chip set which includes the 83c690 and 83b692 as shown in figure 1-1. figure 1-2 provides a functional block diagram of the 83C694d chip itself. 1.2 features features of the 83C694d include: twisted-pair interface solution for ieee 802.3 10baset standard compatible with ethernet ii (10base5) and cheapernet (10base2) ieee 802.3 stand- ards smart squelch ? digital noise filter at receive and collision inputs to reject noise and digital noise on twisted-pair receive inputs. direct connection to the transceiver (aui) ca- ble 16v fault protection at the aui transmitter in- terface 10 mbps manchester encoding/ decoding with receive clock recovery low power, 1.25 m cmos technology ttl/mos-compatible controller interface externally-selectable half- or full-step modes of operation at aui tx outputs loopback capability for diagnostics single station interface operation link test generation and digital equalization for twisted-pair transmitter automatic phase detection aui/tp autoselect built-in led drivers for transmit, receive, link test and polarity status indicators 1.3 general description the 83C694d is used for applications where twisted-pair interface (tpi) and/or attachment unit interface (aui) functions are required. its two main functions are to: 1. receive a digital data stream from a low-level input signal and 2. convert a digital output data stream into an analog high-current signal for transmission across a network cable. this means that the 83C694d serves as the logical link between a network cable on one end and a digital controller chip (such as the 83c690) on the other end. to accomplish these two functions, the 83C694d consists of these components: manchester en- coder/decoder, balanced drivers and receivers, on- board crystal oscillator, signal translator, diagnostic circuit, and protocol timers and state machines. the remainder of this data sheet contains the fol- lowing information: section 2 discusses the system architecture in- cluding an explanation of all chip circuits. section 3 provides pin descriptions. section 4 provides dc operating characteristics. section 5 provides ac operating characteristics including interface timing diagrams. section 6 provides the plcc package diagram of this chip. introduction 83C694d 1
83c690 802.3 ethernet lan controller 83C694c manchester encoder/ decoder 83b692 ethernet transceiver 10base2 cheapernet 10baset twisted pair tx+/- rx+/- cd+/- tx+/- cd+/- tpr+/- tpx1+/- tpx2+/- txe txd crs rxd rxc col txc rx+/- transmit filter receive filter aui 10base5 ethernet pc bus interface buffer memory figure 1-1. system block diagram 83C694d introduction 2
encoder crystal oscillator 20 mhz pll decoder collision decoder repeater logic collision detect link beat transmit control jabber detect led drivers aui collision receiver cd+ cd- tpr+ tpr- rx+ rx- tx+ tx- tp receiver aui receiver aui driver tp driver smart squelch link test receive polarity correct lnk lnk lbk lnk col tpol mpe rled xled col rxc crs rxd lbkctl jabber sel tpx+ tpx- lnk mode1 mode1 lbk mode2 txc txe txd jabber digital equalization loopback functions x1 x2 txctl 2 2 figure 1-2. 83C694c block diagram introduction 83C694d 3
2.0 architecture the 83C694d can be used as an aui device or as a twisted-pair interface device. when used in combination tpi/aui applications, the 83C694d is part of a three-device set that implements the complete ieee 802.3-compatible network node electronics (see figure 1-1). the 83c690 ethernet lan controller (elc) and the 83b692 ethernet transceiver (et) comprise the other two devices in the set. the 83c690 provides media access protocol functions and performs buff- er management tasks, while the 83b692 serves as a coaxial cable line driver/receiver and collision detector. the 83C694d twisted-pair interface provides the interface between the 83c690 elc and the 83b692 et. when transmitting, the device converts non-re- turn-to-zero (nrz) data from the controller into manchester encoded data, then sends this data to the transceiver. when receiving, the device reverses the process using an analog phase-locked loop that decodes 10 mbit/sec signals with up to 20 nsec of jitter. when the 83C694d is used as a twisted-pair (tp) interface, its on-chip transmitter and receiver (sepa- rate from the aui inputs and outputs) connect to the network through a transformer and filter. in this application, the 83C694d is used with the 83c690 providing controller and protocol functions, and the 83b692 is not used. the 83C694d twisted-pair interface is comprised of these functional blocks: oscillator manchester encoder and differential driver manchester decoder collision translator loopback capabilities tp differential driver tp differential receiver link test function aui / tp autoselect jabber & sqe test functions status indications the rest of this section describes each of these circuits in more detail, including suggestions, where appropriate, for designing external circuits consis- tent with the 802.3 standard. 2.1 oscillator control is provided either by a 20 mhz, parallel resonant crystal connected between x1 and x2, or by an external clock connected at x1. the oscilla- tors 20 mhz output is divided in half to generate the 10 mhz transmit clock for the ethernet lan controller and to provide the internal clock signals for the encoding and decoding circuits. figure 2-1 provides a diagram of this connection. 20 mhz x1 x2 cl - cp cl = load capacitance specified by crystal manufacturer cp = total parasitic capacitance including: a) 83C694c input capacitance between x1 and x2 (typically 5 pf) b) pc board traces, plated through holes, socket capacitances figure 2-1. crystal connection diagram 83C694d architecture 4
2.2 manchester encoder/ differential driver data encoding and transmission begins when the transmit enable input (txe) goes high and contin- ues as long as the txe remains high. it is essential that the transmit enable and transmit data inputs meet the setup and hold time requirements for the rising edge of the transmit clock. transmission ends when the transmit enable input goes low. the last transition occurs at the center of the bit cell if the last bit is one, or at the boundary of the bit cell if the last bit is zero. the aui differential line driver, which has the ability to drive up to 50 meters of twisted-pair aui/ethernet transceiver cable, provides the emitter-coupled logic (ecl) level signals. with the sel input, select one of two modes, full- step or half-step. when sel is low, tx+ is positive in relation to tx- in the idle state. when sel is high, tx+ and tx- are equal in the idle state. figures 5-1 through 5-3 illustrate aui transmit timing. an exter- nal interface circuit utilizing these signals might resemble figure 2-2. in such a configuration, the transmit interface circuit could utilize an isolation transformer leading to the 83b692 which would then drive the coax signal to the network. another option would use the aui connector which would go to external equipment. 2.3 manchester decoder decoding is accomplished by a differential input receiver circuit and an analog phase-locked loop that separates the manchester-encoded data stream into clock signals and nrz data. to prevent noise at the aui rx+ or rx- input from falsely triggering the decoder, a squelch circuit re- jects signals with pulse widths less than 20 nsec (negative going), or with levels less than -175 mv. when the input exceeds the squelch limits, the analog phase-locked loop locks onto the incoming signal and the 83C694d decodes a data frame. the carrier sense (crs) is activated, and the re- ceive data (rxd) and receive clock (rxc) become available within five bit times. at the end of a frame, when the normal mid-bit transition on the differential input ceases, carrier sense is de-activated. the receive clock remains active for an additional five bit times. figures 5-4 through 5-6 illustrate the receive timing. an external interface circuit for rx+ and rx- might be designed like figure 2-3. to avoid signal corruption caused by excessive voltage fluctuation on the power supply, it is desir- able to externally implement a voltage regulation system consisting of a 5.1-volt zener diode. typi- cally, as shown in figure 2-4, the diodes cathode is connected to pin 20, pin 23, the vcc side of the osr resistor, the vcc side of the bsr resistor, and a 510 w 1 4 -watt resistor which goes from the zener?s cathode to the 12-volt power supply. co a cab l 150w 1% 150w 1% +5v tx+ tx- 83b692 ethernet transceiver figure 2-2. aui transmit path 39.2w 1% aui connector 39.2w 1% 0.1m 0.02m f f 0.02m f rx- or cd- rx+ or cd+ figure 2-3. aui receive path architecture 83C694d 5
it is also helpful to place a decoupling capacitor between the diode?s cathode and ground as shown in figure 2-4. 2.4 collision translator when the 83C694d is used as an aui device, a separate ethernet transceiver detects collisions on the coaxial cable and generates a 10 mhz signal, which is monitored by the 83C694d through the collision detect pins. the presence of the signal activates the collision detect (cd) pin connected to the 83c690 causing the controller to stop transmit- ting. the collision detect output is deactivated within 160 nsec. after the absence of the 10 mhz signal. figure 5-7 illustrates the collision timing. an external interface circuit for cd+ and cd- is de- signed exactly like an external interface for rx+ and rx-. see figure 2-3. 2.5 tp differential driver the tp driver can transmit through up to 100m of unshielded twisted-pair (utp) cable. the driver includes a circuit for transmit equalization, which attenuates low frequency components of the trans- mit waveform. this reduces the zero crossing jitter of the received signal and avoids the use of a receive equalizer. there are two pulse widths transmitted: 50 nsec and 100 nsec. when a pulse width of 100 nsec is sent, both drivers (tpx1+ and tpx2+) turn on and drive a high level. this provides a greater amplitude at the start of the pulse; however, halfway through the pulse tpx2 turns off, thereby reducing the amplitude after 50 ns. a narrow pulse is transmitted at the same amplitude as the first half of the wide pulses. the resistor ratio is calculated to produce the best signal wave shape at the receiving end assuming a utp cable length of 100 meters. figure 2-6 shows the basic twisted-pair transmit path along with its timing and one possible external transmit interface design. typical values for resis- tance on tpx2 pins are 261 w , while tpx1 pins use 65 w . the 2.4k w parallel resistor is used to match the output resistance of the transmi tter to the twisted-pair cable. at the receive end of the cable, a 100 w termination resistor is commonly used. to verify the operation of the circuit, measure the tpx signals differentially. in designing the external circuits to connect the 83C694d transmit outputs to the cable, use a trans- mit filter followed by an isolation transformer and, in the most practical applications, a common mode choke for fcc compliance. the common mode choke may not always be needed in every applica- tion; however, the isolation transformer is always needed and the transmit filter is strongly recom- mended; without it, high frequency radiation may exceed fcc limits. 2.6 tp differential receiver ground (circuit board) cathode anode 10kw 510w (1/4 watt) +12v (circuit board) 31.6kw bsr osr vcc (pin 32) vcc (pin 35) 5.1v zener 83C694c 0.1 f m figure 2-4. zener diode voltage regulation for 12 volts 83C694d architecture 6
the signal received from the unshielded cable can be noisy, so minimum voltage and timing limits must be met before the receiver logic is enabled. a "smart squelch" ? digital noise filter is used in addi- tion to the analog squelch circuit in the receiver. the smart squelch circuit provides extra protection against false collisions and false link connections. if the input polarity is reversed, it will be automat- ically detected and corrected. when this happens, the tpol output pin will go high to signal the controller or to turn off the polarity indicator led. the phase-locked loop and manchester decoder are the same circuits used by the aui receiver. an external interface circuit for tpr+ and tpr- might be designed like figure 2-5. 2.7 loopback function when the loopback input goes high it causes the 83C694d to send serial data from the transmit data input through the encoder, and back through the phase-locked loop and decoder to the receive data output. the transmit driver is in the idle state during loopback mode and the receiver circuitry and colli- sion detection are disabled. loopback can be en- abled during either aui or tp (10baset) operation. transmit data is always looped back during tp operation, simulating the physical broadcast char- acteristic of 802.3 coaxial cable networks. tpr+ tp+ tpr- tp- 100w 1% common mode choke twisted pair cable isolation transformer receive filter figure 2-5. twisted-pair receive path 261w 261w 65w 65w 2.4kw tpx2+ tpx+ tpx1- tpx- tpx1+ tpx2- 100 nsec 50 nsec common mode choke twisted pair cable isolation transformer transmit filter figure 2-6. twisted-pair transmit path and timing architecture 83C694d 7
the 83C694d supports the ieee 802.3 loopback design (section 14.2.1.3) which provides for con- tinuous loopback from transmit to receive in normal operation. this means that transmitted data is al- ways looped back during tp operation, simulating the physical broadcast characteristics of 802.3 co- axial cable networks. 2.8 link test function each tp driver transmits a short positive pulse periodically when it is not sending data as shown in figure 5-4. these pulses are received at the other end of the tp cable, signalling that the link is operating correctly. the time between link test pulses is compared to the expected range at the receiver, to avoid false detection of noise pulses as link test pulses. if the link test fails (no pulses or data received in a fixed time period), then the lnk pin is set high and data transmit and receive on the tp interface is disabled. 2.9 aui/tp autoselect the 83C694d can automatically select which me- dia to transmit and receive on, based on the link test state. if the link test fails, the aui transmitter and receiver are enabled while the tp transmitter, re- ceiver, and loopback are disabled. if link test passes, the aui operation is disabled and tp op- eration is re-enabled. the only exception to this is when mode1 is set low and tp operation is en- abled continuously. 2.10 jabber and sqe test functions if txe is high for greater than 46 ms, the tp transmitter will be disabled and col will go active high. if txe then goes low for more than 368 ms, the tp transmitter will be re- enabled and col will go low. in tp operation, a short pulse will be output on col after each packet is transmitted. this is required as a test of the tp transmit/receive path, and is called sqe test or cd heartbeat. 2.11 status indications to assist in installation and management of the network, indicator leds can be driven by four out- puts from the 83C694d. these show the result of link test, polarity check, and transmit or receive activity. an led test feature is built into the 83C694d. all leds turn on for 2/3 second after a reset to the device. 2.12 test mode three test modes can be selected when the sel pin is set to intermediate voltages. these modes and their corresponding voltages are: internal counter speedup (1.75 v) rxc and rxd enable (2.5 v) output tristate (3.5 v) internal counter speedup is used for fast board- level testing of timed functions such as led power- up blink and link test pulse period. rxc and rxd enable is used to test internal vco functions without using a full data packet receive. output tristate is used during board-level testing to enable short/open testing. it is also used to test other devices resident on the board. this function does not tristate transmit (pins 22-27) or x2 outputs. 83C694d architecture 8
3.0 pin description figure 3-1 illustrates the signal names and pin locations on the 44-pin plcc 83C694d package. table 3-1 lists the signal names and descriptions for the 83C694d. 5432 6 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 18 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 rxd res rxc sel tpol col nc crs lnk gnd gnd lbk txd gnd gnd rled xled x1 x2 txc txe tpx2- tpx1- tpx1+ tx+ osr tpx2+ tx- cap mode1 mode2 vcc vcc vcc vcc nc tst bsr rx- rx+ cd- cd+ tpr- tpr+ figure 3-1. 83C694c 44-pin plcc package drawing pin description 83C694d 9
pin number mnemonic signal name i/o description 1 col collision detect o a 10 mhz (+25%,-15%) signal at the cd inputs (dte mode) produces a logic high at the col output. when no signal is present at the cd inputs, the col output goes low. in 10baset operation, the col output goes high when tpr+ and tpr- are active while a packet is being transmitted on tpx+/tpx-. col also goes high during sqe test or jabber condition. 2 nc no connect i do not connect any circuitry to this pin. 3 rxd receive data o this is the nrz data output from the on-chip decoder and phase-locked loop. this signal should be sampled by the controller at the rising edge of receive clock. a high level is binary "one", a low level is binary "zero". 4 crs carrier sense o crs (dte mode) goes high when valid data is present at the rx+/rx- inputs or tpr+/tpr- inputs. it goes low after the last bit is received at the inputs. 5 res reset/synch i when res is low, all internal nodes are set to a known state except for internal clock distri- bution. this improves testing procedures. normal operation is enabled on the rising edge of res and while res is high. the res pin includes an internal pull up resistor, so it may be left open if unused. 6 rxc receive clock o when the phase-locked loop acquires a valid receive signal, a 10mhz clock signal (recov- ered from receive data) is output on rxc. rxc is low during idle (5 bit times after re- ceive activity stops). 7 sel mode select i when sel is high, tx+ and tx- outputs are at the same voltage in idle state, providing a "zero" differential. when sel is low, tx+ is positive with respect to tx- in idle state. also, three test modes may be selected by setting the sel pin to voltages between low and high levels. refer to section 2.13 for more on test modes. table 3-1. pin description 83C694d pin description 10
pin number mnemonic signal name i/o description 8 lnk twpr link status o if valid data or link test pulses are received on tpr+/tpr-, lnk is low (link status ok). when no data or link test pulses are re- ceived, lnk is high. the lnk pin can sink 10ma to drive an external led. 9 tpol twpr link polarity o tpol is low when positive polarity link test pulses or data packets are received on tpr+/tpr- (normal operation). tpol is high when negative polarity link test pulses or data packets are received (link wiring polarity reversed). when tpol is low, it can sink 10ma to drive an external led. 10 C 13 gnd negative supply pin 10 provides negative supply for analog circuits. pin 11 provides negative supply for digital circuits. pin 12 provides negative sup- ply for digital/pad circuits. pin 13 provides negative supply for vco circuits. 14 rled receive led driver o when active low, rled sinks 10 ma to drive an external led. if no data is received, rled is high. if data is received, rled will go low for approximately 50ms longer than the re- ceived packet length. all led current is controlled internally and requires no external resistors between the chip and an external led. the external led must be connected from +5v to the device pin. if leds are not used, then the four pins can be used as logic out- puts. 15 xled transmit led driver o when active low, xled sinks 10ma to drive an external led. when there is no transmis- sion (txe inactive), xled is high. when data is transmitted, xled g oes active low for ap- proximately 50ms longer than the transmitted packet length. xled does not go active low for link test pulses. table 3-1. pin description cont. pin description 83C694d 11
pin number mnemonic signal name i/o description 16 lbk loopback i a high level enables loopback of txd to rxd/rxc. a low level enables normal trans- mit/receive operation. the lbk pin includes an internal pull-down resistor, so it may be left open if unused. 17 x1 crystal/ext. input i x1 is driven by an external clock frequency source or is connected to one terminal of the 20mhz crystal. the ieee 802.3 standard requires 0.01% ab- solute accuracy on the transmitted signal fre- quency. stray capacitance can shift the crystals frequency out of range, causing it to exceed the 0.01% tolerance. to remedy this, extra load capacitance may be added. to determine the amount of capacitance to add, measure the board capacitance and the capacitance between the x1 and x2 pins. then add these values together, and subtract them from the crystals required load capaci- tance. (refer to figure 2-1.) 18 x2 crystal feedback o this output is connected to the other term inal of the 20mhz crystal. if x1 is driven with an external source, x2 must be left open. 19 txd transmit data i txd is sampled on the rising edge of txc when txe is high. the nrz data input here is encoded and transmitted on tx+/tx- or tpx+/tpx- as a differential signal. 20 txc transmit clock o this is a 10mhz clock signal derived from the internal 20mhz oscillator. it is enabled except when res is low and mpe is high. 21 txe transmit enable i txe enables encoding and transmission of the data input via txd. it is sampled on the rising edge of txc. 22 tpx2- twpr transmit o tpx2- is used for 10baset only. it is the low current negative output pin. see tpx1+ for details. 23 tpx1- twpr transmit o tpx1- is used for 10baset only. it is the high current negative output pin. see tpx1+ for details. table 3-1. pin description cont. 83C694d pin description 12
pin number mnemonic signal name i/o description 24 tpx1+ twpr transmit o in 10baset operation, data input via txd is encoded and then transmitted on tpx pins. when transmit and receive are idle, link test pulses are periodically transmitted via tpx. the tpx pins are connected to the twisted- pair medium via a transformer and filter, and use 5 external resistors for waveshaping as shown in figure 2-6. tpx1+ is the high cur- rent positive output pin. 25 tpx2+ twpr transmit o tpx2+ is used for 10baset only. it is the low current positive output pin. see tpx1+ for details. 26 27 tx- tx+ aui transmit o in aui mode, tx+ and tx- transmit manches- ter encoded data differentially to an external transceiver. each output requires an external pull-up resistor of 150 w 1% to +5v as shown in figure 2-2. 28 osr vco bias resistor i a resistor from osr to +5v biases the internal vco current. nominal value is 31.6 k w 1%. 29 cap pll filter cap i a capacitor (nominal value .02 m f) from cap to ground is used as part of the filter for the internal phase-locked loop. 30 mode1 mode select 1 i with mode1 low, tp mode is always se- lected. no link test pulses are transmitted or required on rx+/-. when mode1 is high, aui mode is selected at power on. when mode1 is connected to res, 10baset mode is se- lected at power on. after power on, if mode1 is not low, 10baset mode is automatically selected if lnk goes low (otherwise aui mode is selected). the mode1 pin includes an internal pull-up resistor, so it can be left open if not used. 31 mode2 mode select 2 i when mode2 is low, automatic link polarity correction is disabled (tp mode only). auto- polarity correction is enabled when mode2 is high. the mode2 pin includes an internal pull up resistor, so it may be left open if not used. table 3-1. pin description cont. pin description 83C694d 13
pin number mnemonic signal name i/o description 32, 33, 34, 35 vcc positive supply pin 32 is positive supply to the vco. pin 33 is positive supply for digital and transmit cir- cuits. pin 34 is positive supply for digital cir- cuits. pin 35 is positive supply for receive circuits. 36 nc not connected do not connect to this pin. 37 tst test input i this pin must be tied low. 38 bsr bias resistor i a resistor from bsr to vcc sets the internal bias levels. nominal value is 10k w 1% resis- tor connected externally to +5v. if bsr is tied low, a low power mode is enabled and trans- mit/receive is disabled. 39 40 rx- rx+ aui receive i in aui mode, the manchester encoded data from an external transceiver is received on rx+/rx-. after timing recovery and decoding, it is output to the controller on rxd. with the standard 78 w transceiver aui cable, the dif- ferential input must be externally terminated. this requirement can be satisfied by connect- ing two 39.2 w 1% resistors in series with an optional 0.1 m f common mode bypass ca- pacitor as shown in figure 2-3. matched ca- pacitors can also be added to protect the inputs from external faults. 41 42 cd- cd+ aui collision i in aui mode, a 10 mhz collision presence signal from an external transceiver is received on cd+/cd-. the col pin is then output high. the collision differential inputs, cd+ and cd-, must be terminated in the same manner as the receive inputs, rx+ and rx-. see figure 2-3 for information on this design. table 3-1. pin description cont. 83C694d pin description 14
pin number mnemonic signal name i/o description 43 44 tpr- tpr+ twisted-pair receive i in 10baset mode, manchester encoded data is received via tpr+/tpr-. after timing re- covery and decoding it is output to the con- troller on rxd. tpr+/tpr- are connected to the twisted-pair medium through a trans- former and filter. a 100 w termination resistor is generally used before the circuit connects to the receive sig- nal lines, tpr+ and tpr- inputs. see figure 2-5 for information on this design. the 83C694d automatically corrects for a misconnection of the + and - interface allow- ing operation without having to correct the wiring. table 3-1. pin description cont. pin description 83C694d 15
4.0 dc electrical specifications 4.1 absolute maximum ratings supply voltage (vcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v ttl input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C 5.5v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 C 5.5v differential output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C 16v differential output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 ma storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c (-85f) to 150 (302f) absolute maximum ratings indicate limits beyond which permanent damage may occur. continuous operation at these limits is not recommended; operation should be limited to conditions specified under dc operating characteristics. 4.2 recommended operating conditions supply voltage (vcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c (32f) to 70c (158f) 4.3 dc operating characteristics ta = 0c (32f) to 70c (158f) vcc = +5v 5% note all currents into device pins are positive. all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. symbol characteristic min max units conditions vih input high voltage (ttl and x1) 1 input high voltage (sel) 2.0 4.5 C C v v C C vil input low voltage (ttl, x1, sel) C0.8vC iih input high current (ttl, x1, sel) input high current (rx and cd ) ? ? 50 500 m a m a vin = vcc iil input low current (ttl, x1 and sel) input low current (rx and cd ) ? ? -50 -500 m a m a vin = 0.5v vcl input clamp voltage (ttl) ? -1.2 v iin = -12ma voh output high voltage (rxd, rxc, crs, txc, col, x2 and leds) 2 3.5 ? v ioh = -100 m a 83C694d dc electrical specifications 16
symbol characteristic min max units conditions vol output low voltage (rxd, rxc, crs, txc, col) output low voltage (x2) output low voltage (leds) C C C 0.5 0.7 0.5 v v v iol = 8ma iol = 2 ma iol output low current (leds) 10 25 ma 2v vol 4v ios output short circuit current (rxd, rxc, crs, txc, col) -40 -200 ma ? vod differential output voltage (tx ) 500 1200 mv 78 w termination and 150 w from each output to vcc vob differential output voltage imbalance (tx ) ? 40 mv 78 w termination and 150 w from each output to vcc voh output high voltage (tpx1 ) output high voltage (tpx2 ) vcc - 0.6 vcc - 0.75 ? ? v v ioh = -30ma ioh = -14 ma vol output low voltage (tpx1 ) output low voltage (tpx2 ) ?0.6 0.75 v v ioh = 30 ma ioh = 14 ma vds differential squelch threshold (rx , cd ) differential squelch threshold (tpr ) -175 300 -300 500 mv mv peak ? ? vcm differential input common mode voltage (rx , cd ) 05.25v? icc power supply current ? 100 ma loopback active at 10 mbit/sec table 4-1. dc operating characteristics 1 ttl inputs are txe, txd, lbk, mode1, mode2, and res. 2 led drivers are rled, xled, lnk, and tpol. dc electrical specifications 83C694d 17
5.0 ac operating characteristics ta = 0c (32f) to 70c (158f) vcc = 5v 5% note all typical values are given for vcc = 5v and ta = 25c (77f). symbol parameter min typ max units oscillator specification t xth x1 rising edge to transmit clock high 8 C 25 nsec t xtl x1 rising edge to transmit clock low 8 C 25 nsec transmit specification t tcd transmit clock duty cycle at 50% (10 mhz) 42 50 58 % t tcr transmit clock rise time (20 to 80%) C C 8 nsec t tcf transmit clock fall time (20 to 80%) C C 8 nsec t tds transmit data setup time to transmit clock rising edge 20 C C nsec t tdh transmit data hold time from transmit clock rising edge 0 C C nsec t tes transmit enable setup time to transmit clock rising edge 20 C C nsec t teh transmit enable hold time from transmit clock rising edge 0 C C nsec t tod transmit output delay from transmit clock rising edge C C 60 nsec t tor transmit output rise time (20% to 80%) (tx ) ? ? 8 nsec transmit output rise time (tpx ) ? 4.5 ? nsec t tof transmit output fall time (80% to 20%) (tx ) ? ? 8 nsec transmit output fall time (tpx ) ? 4.5 ? nsec t toj transmit output jitter (tx )? 0.25 ? nsec t toh transmit output high before idle in half step mode 200 ? ? nsec t toi transmit output idle time in half step mode ? ? 350 nsec t ltpw link test pulse width 100 nsec receive specification t rcd receive clock duty cycle at 50% (10 mhz) 40 50 60 % t rcr receive clock rise time (20% to 80%) ? ? 8 nsec t rcf receive clock fall time (20% to 80%) ? ? 8 nsec t rdr receive data rise time (20% to 80%) ? ? 8 nsec t rdf receive data fall time (80% to 20%) ? ? 8 nsec t rds receive data stable from receive clock rising edge 40 ? ? nsec t cson carrier sense turn on delay (aui) ? ? 60 nsec carrier sense turn on delay (tp) ? ? 300 nsec t csoff carrier sense turn off delay (aui) ? ? 160 nsec carrier sense turn off delay (tp) ? ? 160 nsec 83C694d ac operating characteristics 18
symbol parameter min typ max units t dat decoder acquisition time (aui) C C 700 nsec decoder acquisition time (tp) C C 950 nsec t drej differential inputs rejection pulse width (aui) 8 25 35 nsec differential inputs rejection pulse width (tp) 8 20 30 nsec t rd receive throughput delay C C 200 nsec collision specification t colon collision turn on delay (aui) C C 60 nsec collision turn on delay (tp) C C 900 nsec t coloff collision turn off delay (aui) 100 C 160 nsec collision turn off delay (tp) C C 160 nsec t sqeon sqe test start delay (tp) 0.6 1.0 1.6 usec t sqed sqe test duration (tp) 0.5 1.0 1.5 usec loopback specification t lbs loopback setup time 35 C C nsec t lbh loopback hold time 350 C C nsec 10baset protocol timers link test transmit period 9.8 C 11.5 msec link loss / link test max. 78 C 92 msec link test min. 4.9 C 5.8 msec jabber on (transmit inhibit) 39 C 46 msec jabber off (transmit reCenable) 314 C 368 msec table 5-1. ac operating characteristics ac operating characteristics 83C694d 19
5.1 timing diagrams figures 5C1 through 5C9 illustrate all timings. table 5C2 lists all timing diagrams. figure number title 5C1 transmit timing C start of transmission 5C2 transmit timing C end of transmission (last bit = 0) 5C3 transmit timing C end of transmission (last bit = 1) 5C4 transmit timing C link test pulse 5C5 receive timing C start of packet 5C6 receive timing C end of packet (last bit = 0) 5C7 receive timing C end of packet (last bit = 1) 5C8 collision timing (aui) 5C9 collision timing (tp) 5C10 sqe test timing 5C11 loopback timing 5C12 test loads table 5C2. 83C694d timing diagrams 83C694d ac operating characteristics 20
t t tdh tod 1.5v 1.5v 1.5v 1.5v txc txe txd tx+ tx- tpx2+ tpx1+ tpx1- tpx2- tes t t tds figure 5-1. tx timing - start of transmission figure 5-2. tx timing - end of transmission (last bit=0) ac operating characteristics 83C694d 21
1 1 1 10 1 1.5v 1.5v txc txe txd 1 1 1 1 0 0 1 1 tx+ tx- t toh t toi teh t tpx2+ tpx1+ tpx1- tpx2- figure 5-3. tx timing - end of transmission (last bit=1) txc tpx2+ tpx1+ tpx1- tpx2- ltp t figure 5-4. tx timing - link test pulse 83C694d ac operating characteristics 22
1 0 10 10 1 0 1 0 10 10 10 1 1 0 1 0 10 10 10 1 1.5v 1.5v 1.5v t drej first bit decoded t rds t rds t dat rxd rxc crs rx+/rx- or tprx+/tprx- t cson figure 5-5. receive timing - start of packet 10 10 0 10 1 0 0 crs rxc rxd 5 extra clocks t csoff t rd 1.5v rx+/rx- or tprx+/tprx- figure 5-6. receive timing - end of packet (last bit = 0) ac operating characteristics 83C694d 23
10 10 1 5 extra clocks 10 10 1 rx+ rx- crs rxc rxd t csoff figure 5-7. receive timing - end of packet (last bit = 1) t coloff t colon 1.5v cd+ cd- col 1.5v figure 5-8. collision timing (aui) 83C694d ac operating characteristics 24
t t colon coloff col txe tprx+ tprx- figure 5-9. collision timing (tp) txe t sqed t sqeon col figure 5-10. sqe test timing ac operating characteristics 83C694d 25
1.5v 1.5v 1.5v 1.5v t lbs t lbh lbk txe figure 5-11. loopback timing tx + tpx1+ tpx2+ tx- tpx1- tpx2- r* 150 ohm 237 ohm 237 ohm 50 pf ttl/m os outp uts _1% + 27 h** m 150 ohm 59 ohm 59 ohm +5v +5v * r = 73 ohm + 1% and r = 83 ohm + 1% m m engineering 64103) are recommended for application use. ** 27 h + 1% inductor is used for test purposes. 100 h tranformers (valor lt 1101, or pulse figure 5-12. test loads 83C694d ac operating characteristics 26
6.0 package description figure 6-1 illustrates the 44-pin plcc package for the 83C694d. refer to table 6-1 for the dimensions given in this figure. figure 6-1. 44-pin plcc package diagram package description 83C694d 27
table 6-1 provides acceptable ranges for the codes shown in figure 6-1. all dimensions are in inches. code dimension ranges a .160 C .188 a1 .090 C .120 b .013 C .021 b1 .026 C .032. b2 .025 min c .020 C .045 d/e .685 C .695 d1/e1 .650 C .656 d2/e2 .600 C .630 d3/e3 .500 ref e .050 bsc f .042 C .060 g .042 C .048 j .000 C .028 r .025 C .045 table 6-1. plcc package dimensions notes: 1. coplanarity is .004" maximum 2. tolerance on the position of the leads is .007"maximum 3. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is .010" 83C694d package description 28
index ! 83b692 ethernet transceiver, 4 83c690 ethernet lan controller, 4 83C694d functional blocks, 4 as twisted-pair interface, 4 pin package, 27 a absolute maximum ratings, 16 ac operating characteristics, 18 - 20 architecture, 4 - 8 aui collision, 14 aui differential line driver, 5 design notes, 5 aui receive, 14 aui transmit, 13 aui/tp autoselect, 8 autoselect, 8 b bias resistor, 14 bsr, 14 c cap, 13 carrier sense, 10 carrier sense (crs), 5 cd-/cd+, 14 col, 10 collision detect, 10 collision tran slator, 6 crs, 10 crystal accuracy, 12 crystal feedback, 12 crystal/ext. input, 12 d dc electrical specifications, 16 - 17 recommended operating conditions, 16 dc operating characteristics, 16 decoding, 5 differential driver, 5 f features, 1 g general description, 1 gnd, 11 i indicator leds, 8 internal counter speedup, 8 introduction, 1 j jabber, 8 l lbk, 12 led test functions, 8 link test function, 8 lnk, 11 loopback, 12 loopback function, 7 m main functions, 1 manchester decoder, 5 manchester encoder, 5 manchester encoding, 4 mode select, 10 mode select 1, 13 mode select 2, 13 mode1, 13 mode2, 13 n negative supply, 11 nrz data conversion, 4 o oscillator, 4 osr, 13 output tristate, 8 p phase-locked loop, 5, 7 plcc/pqfp package, 9 pll filter cap, 13 positive supply, 14 prevention of voltage fluctuation, 5 pulse widths transmitted, 6 r receive clock, 10 receive data, 10 receive led driver, 11 res, 10 reset/synch, 10 rled, 11 rx-/rx+, 14 rxc, 10 rxc & rxd enable, 8 rxd, 10 s sel, 10 smart squelch, 1, 7 sqe test functions, 8 status indications, 8 t test modes, 8 timing diagrams, 20 tp differential driver, 6 design notes, 6 tp differential receiver, 7 tpol, 11 tpr-/tpr+, 15 tpx1+, 13 tpx1-, 12 tpx2+, 13 tpx2-, 12 transmit clock, 12 transmit data, 12 transmit enable, 12 transmit led driver, 11 tst, 14 twisted-pair interface, 4 twisted-pair link polarity, 11 twisted-pair link status, 11 index 83C694d 29
twisted-pair receive, 15 twisted-pair transmit, 12 - 13 tx-/tx+, 13 txc, 12 txd, 12 txe, 12 typical tpx pin values, 6 u utp, 6 v vcc, 14 vco bias resistor, 13 x x1, 12 x2o, 12 xled, 11 z zener diode 5-volt supply, 5 83C694d index 30

▲Up To Search▲

Price & Availability of 83C694

	To Download 83C694 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .